THM1176InstrumentDriver  1.0
C++ API for Metrolab THM1176
CTHM1176StatusTest.cpp
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1 // Copyright (c) 2020 Metrolab Technology S.A., Geneva, Switzerland (www.metrolab.com)
2 // See the included file LICENSE.txt for the licensing conditions.
3 
7 
8 #include "gtest/gtest.h"
9 #include "THM1176TestUtilities.h"
10 #include <ctime>
11 
12 using namespace MTL::Instrument;
13 using namespace MTL::Instrument::THM1176Types;
14 
16 class CTHM1176StatusTest : public ::testing::Test
17 {
18 protected:
19  static THM1176_TEST_RESOURCE_MANAGER_CLASS * pResourceManager;
21 
22  static void SetUpTestCase()
23  {
24  ASSERT_EQ(true, ConnectToTHM1176(pResourceManager, pTHM1176));
25  ASSERT_NE(nullptr, pResourceManager);
26  ASSERT_NE(nullptr, pTHM1176);
27  ASSERT_EQ(true, pTHM1176->IsOpen());
28  ASSERT_EQ(true, pTHM1176->Reset());
29  }
30 
31  static void TearDownTestCase()
32  {
33  delete pTHM1176;
34  pTHM1176 = nullptr;
35  delete pResourceManager;
36  pResourceManager = nullptr;
37  }
38 };
39 THM1176_TEST_RESOURCE_MANAGER_CLASS * CTHM1176StatusTest::pResourceManager = nullptr;
41 
43 TEST_F(CTHM1176StatusTest, StatusSetEnableRegister)
44 {
45  CSCPIBuffer l_ReadBuffer;
46 
47  {
48  uStatusByte l_DisableMask, l_EnableMask;
49  l_DisableMask.RawSTB = 0xff;
50  l_EnableMask.StatusByte.EAV = 1;
51  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
52  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
53  EXPECT_EQ("4\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
54 
55  l_DisableMask = l_EnableMask;
56  l_EnableMask.RawSTB = 0x00;
57  l_EnableMask.StatusByte.QSB = 1;
58  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
59  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
60  EXPECT_EQ("8\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
61 
62  l_DisableMask = l_EnableMask;
63  l_EnableMask.RawSTB = 0x00;
64  l_EnableMask.StatusByte.MAV = 1;
65  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
66  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
67  EXPECT_EQ("16\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
68 
69  l_DisableMask = l_EnableMask;
70  l_EnableMask.RawSTB = 0x00;
71  l_EnableMask.StatusByte.ESB = 1;
72  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
73  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
74  EXPECT_EQ("32\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
75 
76  l_DisableMask = l_EnableMask;
77  l_EnableMask.RawSTB = 0x00;
78  l_EnableMask.StatusByte.RQS = 1;
79  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
80  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
81  EXPECT_EQ("0\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end())); // Special case; see IEEE 488.2 10.34.3 and 10.35.3.
82 
83  l_DisableMask = l_EnableMask;
84  l_EnableMask.RawSTB = 0x00;
85  l_EnableMask.StatusByte.OSB = 1;
86  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
87  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
88  EXPECT_EQ("128\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
89 
90  l_DisableMask = l_EnableMask;
91  l_EnableMask.RawSTB = 0x00;
92  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, l_DisableMask.RawSTB, l_EnableMask.RawSTB));
93  ASSERT_EQ(true, pTHM1176->Write("*SRE?") && pTHM1176->Read(l_ReadBuffer));
94  EXPECT_EQ("0\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
95  }
96  {
97  uStandardEvent l_DisableMask, l_EnableMask;
98  l_DisableMask.RawSE = 0xff;
99  l_EnableMask.StandardEvent.OperationComplete = 1;
100  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
101  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
102  EXPECT_EQ("1\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
103 
104  l_DisableMask = l_EnableMask;
105  l_EnableMask.RawSE = 0x00;
106  l_EnableMask.StandardEvent.QueryError = 1;
107  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
108  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
109  EXPECT_EQ("4\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
110 
111  l_DisableMask = l_EnableMask;
112  l_EnableMask.RawSE = 0x00;
113  l_EnableMask.StandardEvent.DeviceDependentError = 1;
114  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
115  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
116  EXPECT_EQ("8\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
117 
118  l_DisableMask = l_EnableMask;
119  l_EnableMask.RawSE = 0x00;
120  l_EnableMask.StandardEvent.ExecutionError = 1;
121  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
122  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
123  EXPECT_EQ("16\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
124 
125  l_DisableMask = l_EnableMask;
126  l_EnableMask.RawSE = 0x00;
127  l_EnableMask.StandardEvent.CommandError = 1;
128  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
129  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
130  EXPECT_EQ("32\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
131 
132  l_DisableMask = l_EnableMask;
133  l_EnableMask.RawSE = 0x00;
134  l_EnableMask.StandardEvent.PowerOn = 1;
135  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
136  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
137  EXPECT_EQ("128\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
138 
139  l_DisableMask = l_EnableMask;
140  l_EnableMask.RawSE = 0x00;
141  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, l_DisableMask.RawSE, l_EnableMask.RawSE));
142  ASSERT_EQ(true, pTHM1176->Write("*ESE?") && pTHM1176->Read(l_ReadBuffer));
143  EXPECT_EQ("0\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
144  }
145  {
146  uOPERation l_DisableMask, l_EnableMask;
147  l_DisableMask.RawOPER = 0xffff;
148  l_EnableMask.OPERation.CALibrating = 1;
149  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister, l_DisableMask.RawOPER, l_EnableMask.RawOPER));
150  ASSERT_EQ(true, pTHM1176->Write(":STAT:QUES:ENAB?") && pTHM1176->Read(l_ReadBuffer));
151  EXPECT_EQ("1\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
152 
153  l_DisableMask = l_EnableMask;
154  l_EnableMask.RawOPER = 0x0000;
155  l_EnableMask.OPERation.RANGing = 1;
156  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister, l_DisableMask.RawOPER, l_EnableMask.RawOPER));
157  ASSERT_EQ(true, pTHM1176->Write(":STAT:QUES:ENAB?") && pTHM1176->Read(l_ReadBuffer));
158  EXPECT_EQ("4\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
159 
160  l_DisableMask = l_EnableMask;
161  l_EnableMask.RawOPER = 0x0000;
162  l_EnableMask.OPERation.MEASuring = 1;
163  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister, l_DisableMask.RawOPER, l_EnableMask.RawOPER));
164  ASSERT_EQ(true, pTHM1176->Write(":STAT:QUES:ENAB?") && pTHM1176->Read(l_ReadBuffer));
165  EXPECT_EQ("16\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
166 
167  l_DisableMask = l_EnableMask;
168  l_EnableMask.RawOPER = 0x0000;
169  l_EnableMask.OPERation.WaitingForTRIGger = 1;
170  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister, l_DisableMask.RawOPER, l_EnableMask.RawOPER));
171  ASSERT_EQ(true, pTHM1176->Write(":STAT:QUES:ENAB?") && pTHM1176->Read(l_ReadBuffer));
172  EXPECT_EQ("32\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
173 
174  l_DisableMask = l_EnableMask;
175  l_EnableMask.RawOPER = 0x0000;
176  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister, l_DisableMask.RawOPER, l_EnableMask.RawOPER));
177  ASSERT_EQ(true, pTHM1176->Write(":STAT:QUES:ENAB?") && pTHM1176->Read(l_ReadBuffer));
178  EXPECT_EQ("0\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
179  }
180  {
181  uQUEStionable l_DisableMask, l_EnableMask;
182  l_DisableMask.RawQUES = 0xffff;
183  l_EnableMask.QUEStionable.Frequency = 1;
184  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, l_DisableMask.RawQUES, l_EnableMask.RawQUES));
185  ASSERT_EQ(true, pTHM1176->Write(":STAT:OPER:ENAB?") && pTHM1176->Read(l_ReadBuffer));
186  EXPECT_EQ("32\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
187 
188  l_DisableMask = l_EnableMask;
189  l_EnableMask.RawQUES = 0x0000;
190  l_EnableMask.QUEStionable.Overrange = 1;
191  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, l_DisableMask.RawQUES, l_EnableMask.RawQUES));
192  ASSERT_EQ(true, pTHM1176->Write(":STAT:OPER:ENAB?") && pTHM1176->Read(l_ReadBuffer));
193  EXPECT_EQ("512\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
194 
195  l_DisableMask = l_EnableMask;
196  l_EnableMask.RawQUES = 0x0000;
197  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, l_DisableMask.RawQUES, l_EnableMask.RawQUES));
198  ASSERT_EQ(true, pTHM1176->Write(":STAT:OPER:ENAB?") && pTHM1176->Read(l_ReadBuffer));
199  EXPECT_EQ("0\n", std::string(l_ReadBuffer.begin(), l_ReadBuffer.end()));
200  }
201 }
202 
204 TEST_F(CTHM1176StatusTest, StatusGetSingleRegister)
205 {
206  uStatusByte l_StatusByte;
207  uStandardEvent l_StandardEvent;
208  uOPERation l_Operation;
209  uQUEStionable l_Questionable;
210 
211  // Test getting enable registers.
212  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, 0xff, 0x01));
213  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, 0xff, 0x02));
214  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, 0xff, 0x04));
215  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister,0xff, 0x08));
216 
217  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusByte, kStatusEnable), l_StatusByte.RawSTB));
218  EXPECT_EQ(0x01, l_StatusByte.RawSTB);
219  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStandardEventStatusRegister, kStatusEnable), l_StandardEvent.RawSE));
220  EXPECT_EQ(0x02, l_StandardEvent.RawSE);
221  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusOperationStatusRegister, kStatusEnable), l_Operation.RawOPER));
222  EXPECT_EQ(0x04, l_Operation.RawOPER);
223  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusQuestionableStatusRegister, kStatusEnable), l_Questionable.RawQUES));
224  EXPECT_EQ(0x08, l_Questionable.RawQUES);
225 
226  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, 0xff, 0x00));
227  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, 0xff, 0x00));
228  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, 0xff, 0x00));
229  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister,0xff, 0x00));
230 
231  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusByte, kStatusEnable), l_StatusByte.RawSTB));
232  EXPECT_EQ(0x00, l_StatusByte.RawSTB);
233  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStandardEventStatusRegister, kStatusEnable), l_StandardEvent.RawSE));
234  EXPECT_EQ(0x00, l_StandardEvent.RawSE);
235  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusOperationStatusRegister, kStatusEnable), l_Operation.RawOPER));
236  EXPECT_EQ(0x00, l_Operation.RawOPER);
237  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusQuestionableStatusRegister, kStatusEnable), l_Questionable.RawQUES));
238  EXPECT_EQ(0x00, l_Questionable.RawQUES);
239 
240  // Perform a measurement, with an overrun error, to set some status bits.
241  std::string l_Command = "*RST;*CLS;*ESE 8;:STAT:OPER:ENAB 16;:STAT:QUES:ENAB 32;:SENS:AUTO 0;UPP MAX;:TRIG:SOUR TIM;TIM MIN;COUN 2;:AVER:COUN 10;:INIT;*OPC";
242  ASSERT_EQ(true, pTHM1176->Write(l_Command));
243 
244  // Test getting condition registers.
245  ASSERT_EQ(false, pTHM1176->StatusGet(sStatusRegister(kStatusByte, kStatusCondition), l_StatusByte.RawSTB));
246 
247  ASSERT_EQ(false, pTHM1176->StatusGet(sStatusRegister(kStandardEventStatusRegister, kStatusCondition), l_StandardEvent.RawSE));
248 
249  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusOperationStatusRegister, kStatusCondition), l_Operation.RawOPER));
250  EXPECT_EQ(0, l_Operation.RawOPER);
251 
252  std::vector<sError> l_ErrorList = pTHM1176->CurrentErrorList();
253  EXPECT_EQ(1, l_ErrorList.size());
254  EXPECT_EQ(206, l_ErrorList[0].Code);
255  EXPECT_EQ("Timer was overrun", l_ErrorList[0].Description);
256  EXPECT_EQ(":STAT:OPER:COND?", l_ErrorList[0].Context);
257 
258  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusQuestionableStatusRegister, kStatusCondition), l_Questionable.RawQUES));
259  EXPECT_EQ(0, l_Questionable.RawQUES);
260 
261  // Test getting event registers.
262  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusByte, kStatusEvent), l_StatusByte.RawSTB));
263  EXPECT_EQ(0, l_StatusByte.StatusByte.EAV);
264  EXPECT_EQ(1, l_StatusByte.StatusByte.QSB);
265  EXPECT_EQ(0, l_StatusByte.StatusByte.MAV);
266  EXPECT_EQ(1, l_StatusByte.StatusByte.ESB);
267  EXPECT_EQ(0, l_StatusByte.StatusByte.RQS);
268  EXPECT_EQ(1, l_StatusByte.StatusByte.OSB);
269 
270  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStandardEventStatusRegister, kStatusEvent), l_StandardEvent.RawSE));
271  EXPECT_EQ(1, l_StandardEvent.StandardEvent.OperationComplete);
272  EXPECT_EQ(0, l_StandardEvent.StandardEvent.QueryError);
273  EXPECT_EQ(1, l_StandardEvent.StandardEvent.DeviceDependentError);
274  EXPECT_EQ(0, l_StandardEvent.StandardEvent.ExecutionError);
275  EXPECT_EQ(0, l_StandardEvent.StandardEvent.CommandError);
276  EXPECT_EQ(0, l_StandardEvent.StandardEvent.PowerOn);
277 
278  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusOperationStatusRegister, kStatusEvent), l_Operation.RawOPER));
279  EXPECT_EQ(0, l_Operation.OPERation.CALibrating);
280  EXPECT_EQ(1, l_Operation.OPERation.RANGing);
281  EXPECT_EQ(1, l_Operation.OPERation.MEASuring);
282  EXPECT_EQ(1, l_Operation.OPERation.WaitingForTRIGger);
283 
284  ASSERT_EQ(true, pTHM1176->StatusGet(sStatusRegister(kStatusQuestionableStatusRegister, kStatusEvent), l_Questionable.RawQUES));
285  EXPECT_EQ(1, l_Questionable.QUEStionable.Frequency);
286  EXPECT_EQ(0, l_Questionable.QUEStionable.Overrange);
287 }
288 
290 TEST_F(CTHM1176StatusTest, StatusGetMultipleRegisters)
291 {
292  RegisterList l_Registers;
293  StatusValues l_Status;
294 
295  // Test getting enable registers.
296  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, 0xff, 0x01));
297  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, 0xff, 0x02));
298  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, 0xff, 0x04));
299  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister,0xff, 0x08));
300 
301  l_Registers.clear();
302  l_Registers.push_back(sStatusRegister(kStatusByte, kStatusEnable));
306  l_Status.clear();
307 
308  ASSERT_EQ(true, pTHM1176->StatusGet(l_Registers, l_Status));
309  EXPECT_EQ(4, l_Status.size());
310  EXPECT_EQ(0x01, l_Status[0]);
311  EXPECT_EQ(0x02, l_Status[1]);
312  EXPECT_EQ(0x04, l_Status[2]);
313  EXPECT_EQ(0x08, l_Status[3]);
314 
315  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusByte, 0xff, 0x00));
316  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStandardEventStatusRegister, 0xff, 0x00));
317  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, 0xff, 0x00));
318  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister,0xff, 0x00));
319 
320  ASSERT_EQ(true, pTHM1176->StatusGet(l_Registers, l_Status));
321  EXPECT_EQ(4, l_Status.size());
322  EXPECT_EQ(0x00, l_Status[0]);
323  EXPECT_EQ(0x00, l_Status[1]);
324  EXPECT_EQ(0x00, l_Status[2]);
325  EXPECT_EQ(0x00, l_Status[3]);
326 
327  // Perform a measurement, with an overrun error, to set some status bits.
328  std::string l_Command = "*RST;*CLS;*ESE 8;:STAT:OPER:ENAB 16;:STAT:QUES:ENAB 32;:SENS:AUTO 0;UPP MAX;:TRIG:SOUR TIM;TIM MIN;COUN 2;:AVER:COUN 10;:INIT;*OPC";
329  ASSERT_EQ(true, pTHM1176->Write(l_Command));
330 
331  // Test getting condition registers.
332  l_Registers.clear();
333  l_Registers.push_back(sStatusRegister(kStatusByte, kStatusCondition));
337  l_Status.clear();
338 
339  ASSERT_EQ(false, pTHM1176->StatusGet(l_Registers, l_Status));
340 
341  l_Registers.clear();
344  l_Status.clear();
345 
346  ASSERT_EQ(true, pTHM1176->StatusGet(l_Registers, l_Status));
347  EXPECT_EQ(2, l_Status.size());
348  EXPECT_EQ(0x00, l_Status[0]);
349  EXPECT_EQ(0x00, l_Status[1]);
350 
351  std::vector<sError> l_ErrorList = pTHM1176->CurrentErrorList();
352  EXPECT_EQ(1, l_ErrorList.size());
353  EXPECT_EQ(206, l_ErrorList[0].Code);
354  EXPECT_EQ("Timer was overrun", l_ErrorList[0].Description);
355  EXPECT_EQ(":STAT:OPER:COND?;:STAT:QUES:COND?", l_ErrorList[0].Context);
356 
357  // Test getting event registers.
358  l_Registers.clear();
359  l_Registers.push_back(sStatusRegister(kStatusByte, kStatusEvent));
363  l_Status.clear();
364 
365  ASSERT_EQ(true, pTHM1176->StatusGet(l_Registers, l_Status));
366  EXPECT_EQ(4, l_Status.size());
367 
368  uStatusByte l_StatusByte;
369  l_StatusByte.RawSTB = l_Status[0];
370  EXPECT_EQ(0, l_StatusByte.StatusByte.EAV);
371  EXPECT_EQ(1, l_StatusByte.StatusByte.QSB);
372  EXPECT_EQ(0, l_StatusByte.StatusByte.MAV);
373  EXPECT_EQ(1, l_StatusByte.StatusByte.ESB);
374  EXPECT_EQ(0, l_StatusByte.StatusByte.RQS);
375  EXPECT_EQ(1, l_StatusByte.StatusByte.OSB);
376 
377  uStandardEvent l_StandardEvent;
378  l_StandardEvent.RawSE = l_Status[1];
379  EXPECT_EQ(1, l_StandardEvent.StandardEvent.OperationComplete);
380  EXPECT_EQ(0, l_StandardEvent.StandardEvent.QueryError);
381  EXPECT_EQ(1, l_StandardEvent.StandardEvent.DeviceDependentError);
382  EXPECT_EQ(0, l_StandardEvent.StandardEvent.ExecutionError);
383  EXPECT_EQ(0, l_StandardEvent.StandardEvent.CommandError);
384  EXPECT_EQ(0, l_StandardEvent.StandardEvent.PowerOn);
385 
386  uOPERation l_Operation;
387  l_Operation.RawOPER = l_Status[2];
388  EXPECT_EQ(0, l_Operation.OPERation.CALibrating);
389  EXPECT_EQ(1, l_Operation.OPERation.RANGing);
390  EXPECT_EQ(1, l_Operation.OPERation.MEASuring);
391  EXPECT_EQ(1, l_Operation.OPERation.WaitingForTRIGger);
392 
393  uQUEStionable l_Questionable;
394  l_Questionable.RawQUES = l_Status[3];
395  EXPECT_EQ(1, l_Questionable.QUEStionable.Frequency);
396  EXPECT_EQ(0, l_Questionable.QUEStionable.Overrange);
397 }
398 
401 {
402  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusOperationStatusRegister, 0xff, 0x04));
403  ASSERT_EQ(true, pTHM1176->StatusSetEnableRegister(kStatusQuestionableStatusRegister,0xff, 0x08));
404 
405  ASSERT_EQ(true, pTHM1176->StatusPreset());
406 
407  RegisterList l_Registers;
408  StatusValues l_Status;
409  l_Registers.clear();
412  l_Status.clear();
413  ASSERT_EQ(true, pTHM1176->StatusGet(l_Registers, l_Status));
414  EXPECT_EQ(2, l_Status.size());
415  EXPECT_EQ(0x00, l_Status[0]);
416  EXPECT_EQ(0x00, l_Status[1]);
417 
418 }
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::PowerOn
U8 PowerOn
THM1176 has been powered up.
Definition: THM1176Types.h:115
MTL::Instrument::THM1176Types::uStatusByte
Union to access the Status Byte as integer or bit fields.
Definition: THM1176Types.h:81
MTL::Instrument::THM1176Types::RegisterList
List of SCPI status registers.
Definition: THM1176Types.h:66
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::QueryError
U8 QueryError
Error in preceding query.
Definition: THM1176Types.h:110
THM1176TestUtilities.h
Utility functions used to test THM1176 API.
MTL::Instrument::THM1176Types::kStatusOperationStatusRegister
@ kStatusOperationStatusRegister
Operation Status Register.
Definition: THM1176Types.h:41
MTL::Instrument::CSCPIBuffer::end
std::vector< MTL_INSTRUMENT_BUFFER_TYPE >::iterator end()
Return an iterator to the end of the buffer.
Definition: SCPIInstrumentBuffer.h:138
MTL::Instrument::THM1176Types::kStatusCondition
@ kStatusCondition
Condition register.
Definition: THM1176Types.h:47
MTL::Instrument::THM1176Types::kStatusEnable
@ kStatusEnable
Enable register.
Definition: THM1176Types.h:48
MTL::Instrument::THM1176Types::uStandardEvent::StandardEvent
struct MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent StandardEvent
Access the Standard Event Status Register as bit fields.
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::OSB
U8 OSB
OPERation status summary bit.
Definition: THM1176Types.h:95
TEST_F
TEST_F(CTHM1176StatusTest, StatusSetEnableRegister)
Definition: CTHM1176StatusTest.cpp:43
MTL::Instrument::THM1176Types::uOPERation::RawOPER
U16 RawOPER
Access the Operation Status Register as unsigned integer.
Definition: THM1176Types.h:122
MTL::Instrument::THM1176Types::uStatusByte::StatusByte
struct MTL::Instrument::THM1176Types::uStatusByte::sStatusByte StatusByte
Access the Status Byte as bit fields.
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::ExecutionError
U8 ExecutionError
Error detected during command execution.
Definition: THM1176Types.h:112
MTL::Instrument::CTHM1176Instrument< THM1176_TEST_INSTRUMENT_CLASS, THM1176_TEST_RESOURCE_MANAGER_CLASS >
MTL::Instrument::THM1176Types::uQUEStionable::sQUEStionable::Frequency
U16 Frequency
Acquisition buffer or the timed trigger has been overrun.
Definition: THM1176Types.h:148
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::ESB
U8 ESB
Standard Event Status Register summary bit.
Definition: THM1176Types.h:93
MTL::Instrument::CSCPIBuffer::begin
std::vector< MTL_INSTRUMENT_BUFFER_TYPE >::iterator begin()
Return an iterator to the beginning of the buffer.
Definition: SCPIInstrumentBuffer.h:122
MTL::Instrument::THM1176Types::uQUEStionable::RawQUES
U16 RawQUES
Access the Questionable Status Register as unsigned integer.
Definition: THM1176Types.h:141
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::CommandError
U8 CommandError
Error in preceding command.
Definition: THM1176Types.h:113
ConnectToTHM1176
bool ConnectToTHM1176(THM1176_TEST_RESOURCE_MANAGER_CLASS *&rpResourceManager, CTHM1176Instrument< THM1176_TEST_INSTRUMENT_CLASS, THM1176_TEST_RESOURCE_MANAGER_CLASS > *&rpTHM1176)
Connect to a THM1176.
Definition: THM1176TestUtilities.cpp:41
CTHM1176StatusTest::TearDownTestCase
static void TearDownTestCase()
Definition: CTHM1176StatusTest.cpp:31
MTL::Instrument::THM1176Types::uOPERation::sOPERation::WaitingForTRIGger
U16 WaitingForTRIGger
Waiting for trigger.
Definition: THM1176Types.h:133
MTL::Instrument::THM1176Types::uQUEStionable::sQUEStionable::Overrange
U16 Overrange
Measurement was over-range.
Definition: THM1176Types.h:150
MTL::Instrument
Definition: THM1176.h:75
MTL::Instrument::THM1176Types
Definition: THM1176TypeConversions.h:20
MTL::Instrument::THM1176Types::kStatusQuestionableStatusRegister
@ kStatusQuestionableStatusRegister
Questionable Status Register.
Definition: THM1176Types.h:40
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::MAV
U8 MAV
Message Available.
Definition: THM1176Types.h:92
MTL::Instrument::THM1176Types::kStandardEventStatusRegister
@ kStandardEventStatusRegister
Standard Event Status Register.
Definition: THM1176Types.h:39
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::RQS
U8 RQS
ReQuest for Service.
Definition: THM1176Types.h:94
MTL::Instrument::THM1176Types::kStatusByte
@ kStatusByte
Status Byte.
Definition: THM1176Types.h:38
MTL::Instrument::THM1176Types::kStatusEvent
@ kStatusEvent
Event register.
Definition: THM1176Types.h:46
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::EAV
U8 EAV
Error Available in Error / Event Queue.
Definition: THM1176Types.h:90
MTL::Instrument::THM1176Types::uStatusByte::RawSTB
U16 RawSTB
Access the Status Byte as unsigned integer.
Definition: THM1176Types.h:83
MTL::Instrument::THM1176Types::uQUEStionable
Union to access the Questionable Status Register as integer or bit fields.
Definition: THM1176Types.h:139
MTL::Instrument::THM1176Types::StatusValues
List of values returned for several SCPI status registers.
Definition: THM1176Types.h:76
CTHM1176StatusTest::pResourceManager
static THM1176_TEST_RESOURCE_MANAGER_CLASS * pResourceManager
Definition: CTHM1176StatusTest.cpp:19
MTL::Instrument::THM1176Types::uOPERation::sOPERation::RANGing
U16 RANGing
Changing range.
Definition: THM1176Types.h:130
MTL::Instrument::THM1176Types::uQUEStionable::QUEStionable
struct MTL::Instrument::THM1176Types::uQUEStionable::sQUEStionable QUEStionable
Access the Questionable Status Register as bit fields.
MTL::Instrument::THM1176Types::uOPERation
Union to access the Operation Status Register as integer or bit fields.
Definition: THM1176Types.h:120
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::DeviceDependentError
U8 DeviceDependentError
Errors specific to the THM1176, including internal errors.
Definition: THM1176Types.h:111
MTL::Instrument::THM1176Types::sStatusRegister
Complete identification of a SCPI status register.
Definition: THM1176Types.h:52
MTL::Instrument::THM1176Types::uOPERation::sOPERation::CALibrating
U16 CALibrating
Measuring zero-offset.
Definition: THM1176Types.h:128
MTL::Instrument::THM1176Types::uStandardEvent::sStandardEvent::OperationComplete
U8 OperationComplete
*OPC has flagged operation complete
Definition: THM1176Types.h:108
CTHM1176StatusTest
Test THM1176 API: Status manipulation.
Definition: CTHM1176StatusTest.cpp:17
MTL::Instrument::THM1176Types::uOPERation::sOPERation::MEASuring
U16 MEASuring
Measuring magnetic field strength.
Definition: THM1176Types.h:132
MTL::Instrument::THM1176Types::uOPERation::OPERation
struct MTL::Instrument::THM1176Types::uOPERation::sOPERation OPERation
Access the Operation Status Register as bit fields.
MTL::Instrument::CTHM1176Instrument::Reset
bool Reset()
Reset the instrument to power-on configuration.
Definition: THM1176.cpp:2104
CTHM1176StatusTest::pTHM1176
static CTHM1176Instrument< THM1176_TEST_INSTRUMENT_CLASS, THM1176_TEST_RESOURCE_MANAGER_CLASS > * pTHM1176
Definition: CTHM1176StatusTest.cpp:20
MTL::Instrument::THM1176Types::uStandardEvent::RawSE
U16 RawSE
Access the Standard Event Status Register as unsigned integer.
Definition: THM1176Types.h:102
MTL::Instrument::CSCPIBuffer
Instrument Buffer.
Definition: SCPIInstrumentBuffer.h:44
MTL::Instrument::THM1176Types::uStatusByte::sStatusByte::QSB
U8 QSB
QUEStionable status summary bit.
Definition: THM1176Types.h:91
CTHM1176StatusTest::SetUpTestCase
static void SetUpTestCase()
Definition: CTHM1176StatusTest.cpp:22
MTL::Instrument::THM1176Types::uStandardEvent
Union to access the Standard Event Status Register as integer or bit fields.
Definition: THM1176Types.h:100